About this Blog

This blog is an engineering log book; for me to record the progress on my many projects and hopefully to inspire you.

Some projects do not get off the ground, they remain as interesting thoughts, a select few get some work done on them, even fewer get close to completion, and none get completed because unfortunately I subscribe to the theory: "If something ain't broke then it doesn't have enough features". If you'd like to collaborate on some work to get something to a useable state then send me some communications.

Being a blog, posts are listed in chronological order. However I usually have multiple projects on the go and will try to post some of my earlier work. With this in mind I'll try to add labels to each post so all posts relevant to one project can be easily extracted.

Enjoy and happy hacking.

Thursday, September 24, 2009

Naming components in software? - Think about it!

If you are writing a piece of code, especially for other peoples use, think about how you name it. Does it make sense? I have just wasted several hours chasing a bug in some VHDL for an Altera Cyclone III. I want to force the use of carry chains; to inform the synthisizer, pass the signals through a CARRY_SUM buffer that has the ports (Sin, Cin, Sout, Cout). There are a few rules that must be followed for the input logic functions of the signals.
rant begin
Why did the engineer who constructed the CARRY_SUM buffer, put the ports in the opposite order; sum then carry. This engineer has single handedly wasted three hours of my life and I shudder to think how many other people have had the same problem.
end rant;
Unfortunately this is set in stone now, no way to change it, here to annoy me forever. I've posted this in the hope that it will have saved you some precious time, because I couldn't find the solution anywhere else on the interwebs, probably because it makes you feel stupid when you do find the issue and don't want to admit it, hence the rant (it wasn't my fault).